Why Computers Use Binary: The Physics, With Numbers

Overview

Computers use binary for a physical reason rather than a mathematical one. Distinguishing two states is easy in a world of heat, interference and manufacturing variation; distinguishing many states in the same physical range is progressively harder.

That claim is usually argued in the abstract. It does not need to be, because the industry ran the experiment. Flash memory stores multiple bits per cell by dividing one voltage window into more levels, and the cost is precisely measurable.

Single-level cell flash uses two voltage states and survives 50,000 to 100,000 write cycles. Quad-level cell flash divides the same window into sixteen states and survives 100 to 1,000. Each additional bit per cell costs roughly ten times the endurance.

High-speed data transmission shows the same pattern. PCIe 6.0 moved from two signal levels to four, doubling throughput without raising frequency — and gave up 9.5 dB of noise margin, about a third, which made forward error correction mandatory for the first time.

Why Two States Won

The argument for binary is about margins. A circuit does not read an exact voltage; it decides which side of a threshold a voltage falls on. With two states, half the available range can sit either side of that threshold, so a signal can drift enormously and still be read correctly.

Real components make that tolerance necessary. Voltages fluctuate with temperature, adjacent conductors induce interference, power supplies are imperfect, and no two transistors are manufactured identically. Every one of those effects moves a signal away from its intended value.

Adding states shrinks the room for error in direct proportion. Four states quarter the gap between adjacent values; sixteen states divide it by sixteen. The information density rises and the tolerance for physical imperfection falls by the same factor, which is the entire trade in one sentence.

Flash Memory Is the Live Experiment

The theory would be arguable if nobody had tried the alternative. The storage industry tried it comprehensively, because the commercial incentive to store more bits per cell is enormous.

Flash memory stores data as charge trapped in a cell, and the amount of charge determines the voltage read back. Storing one bit means charged or uncharged. Storing more bits means dividing that same voltage window into more distinguishable levels.

Crucially, the window does not get bigger. The physics of the cell fixes it, so every additional bit squeezes twice as many levels into the same range — which makes flash a direct, commercially deployed test of what happens when you abandon two states.

Each Extra Bit Costs 10x Endurance

The results are consistent and steep. Endurance is measured in program/erase cycles — how many times a cell can be written before it degrades past reliable use.

Why 16 Levels in the Same Window Is Hard

The mechanism behind the endurance collapse is worth being specific about, because it explains why the penalty is multiplicative rather than additive.

Writing to a cell means placing a precise amount of charge on it. With two states, the target is approximate — enough charge or not much. With sixteen states, each target is a narrow band, and the write operation must land inside it. Achieving that precision requires more programming pulses and more verification, which stresses the cell harder on every single write.

Retention compounds it. Charge leaks slowly over time, and a cell only needs to drift slightly before a value near one boundary reads as its neighbour. In a two-state cell, drift has to be enormous to flip the reading. In a sixteen-state cell, small drift is sufficient — so the same physical ageing produces errors far sooner.

PCIe 6.0 Went to Four Levels Anyway

Engineers do abandon binary when the alternative is worse, and PCIe 6.0 is the clearest recent example.

Earlier PCIe generations transmitted one bit per unit interval using two voltage levels. PCIe 6.0 adopted PAM4, which carries two bits per interval using four levels — 00, 01, 10 or 11.

The reason is frequency. Doubling the data rate by simply switching twice as fast would double the Nyquist frequency, and channel insertion loss rises sharply with frequency. Doubling the bits per symbol instead achieves the same throughput while keeping insertion loss at roughly the level of PCIe 5.0. Faced with a choice between an unusable channel and a tighter noise margin, the tighter margin wins.

And Paid 9.5 dB for It

The price of that decision is quantified in the specification. Moving from two-level to four-level signalling reduced the noise margin by 9.5 dB — approximately 33%.

The consequence was structural rather than incremental. Starting with PCIe 6.0, forward error correction became mandatory. Previous generations did not require it because two-level signalling had enough margin to be reliable without it.

That is the same trade flash memory makes, in a different domain and with the same shape. More levels bought more throughput in the same physical channel, and the reliability that two states provided for free had to be reconstructed in the protocol.

What Error Correction Actually Buys

Error correction is what makes multi-level systems viable, and it is worth understanding what it costs rather than treating it as a solution.

The technique adds redundant information so that corrupted bits can be detected and reconstructed. It genuinely works — modern QLC drives are reliable products despite cells that would be unusable without it, and heavy error correction is precisely what makes them shippable.

It is not free. Correction consumes bandwidth or capacity that could have carried data, adds latency, and requires processing on both ends. So the real comparison is not sixteen levels against two, but sixteen levels plus substantial error correction machinery against two levels that mostly did not need any. The information gain is real and smaller than the raw level count suggests.

The Ternary Computer That Existed

Binary's dominance was not inevitable, and at least one serious alternative was built and worked.

Setun, constructed at Moscow State University in 1958, used balanced ternary — three states rather than two, representing minus one, zero and plus one. Balanced ternary has genuine mathematical elegance: it represents negative numbers without a separate sign convention, and rounding behaves more naturally than in binary.

It functioned, and around fifty units were produced. It did not spread, because the advantages were mathematical while the disadvantages were physical and industrial. Every component, tool and technique in the growing electronics industry was being optimised for two-state operation, and elegance in representation could not overcome a manufacturing ecosystem converging on the simpler physical case.

Why Reliability Beat Efficiency

The pattern across all of this is consistent: binary is chosen not because it is the most information-dense option but because it is the most tolerant one, and tolerance compounds at scale.

A modern processor contains billions of transistors switching billions of times per second. Even an extraordinarily small per-operation error rate becomes constant failure at that volume, so the margin available on each individual switching event is what determines whether the whole system works at all.

Where engineers do use more states, they do it deliberately, in bounded contexts, and they pay a measurable price — a hundredfold endurance reduction in QLC flash, a 9.5 dB margin loss and mandatory error correction in PCIe 6.0. Both are sound engineering decisions, and both confirm rather than contradict the reason binary dominates everywhere else.

Conclusion

Binary won on noise margins, and the cost of departing from it is measurable rather than theoretical. Flash memory that stores one bit per cell survives up to 100,000 write cycles; flash that divides the same voltage window into sixteen levels survives as few as 100. Each additional bit per cell costs roughly ten times the endurance.

High-speed transmission shows the identical trade. PCIe 6.0 adopted four-level signalling to double throughput without raising frequency, and surrendered 9.5 dB of noise margin — about a third — which made forward error correction mandatory for the first time in the standard's history.

Both are correct engineering decisions, and both are evidence for the same proposition. Multi-level systems work when the capacity or throughput is worth the reliability, and they need substantial machinery to reclaim what two states provided for nothing.

A ternary computer was built in Moscow in 1958 and worked. Binary prevailed anyway, because in a physical world of heat, drift and imperfect components, the system that tolerates the most error scales the furthest.

Data Source and Attribution

Kingston (NAND types)Astera Labs (PAM4)TechInsights (PCIe 6.0)

Flash memory endurance figures for SLC, MLC, TLC and QLC, together with voltage state counts, come from published NAND flash technology specifications and manufacturer documentation; endurance ranges vary by process and vendor and are stated as ranges. PAM4 signalling details, the 9.5 dB noise margin reduction and the mandatory forward error correction requirement come from PCIe 6.0 specification analysis and published engineering commentary. Historical details of the Setun ternary computer reflect the documented record of the Moscow State University project.

FactsFigs reviews, cleans, and cross-checks every source dataset before shaping it into a data story. Each visualization is created and designed in FactsFigs Design Studio — an internal tool developed and owned by FactsFigs — and is the original work of a FactsFigs author, not an AI-generated copy of any existing graphic. Individual assets within a visual may or may not be produced with AI tools, but the design of the visual itself is solely FactsFigs' own.

Figures are typical published specifications and vary by manufacturer, process node and operating conditions.

2026-07-20